Methods and apparatus for adaptively adjusting a data receiver

ABSTRACT

Offsets and timing skews in data signals captured in a data receiver are reduced by adjusting a transition threshold of the data receiver. A data corrector provides a set of adjustment vectors for adjusting the transition threshold of the data receiver. The data receiver may incorporate a trip point adjustor that receives the set of adjustment vectors from the data corrector to adjust its trip point.

RELATED APPLICATIONS

This application is a Divisional of U.S. application Ser. No.10/075,189, filed Feb. 13, 2002, which is incorporated herein byreference.

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to integrated circuit devices such as amemory device. More particularly, the present invention relates to asystem and process for adjusting parameters of data receivers used inintegrated circuit devices.

BACKGROUND OF THE INVENTION

Integrated circuit devices have long been the building blocks for a widevariety of applications. One of the largest applications for integratedcircuits has been in the field of digital computers, where thedevelopment of smaller feature sizes for the integrated circuit hasallowed for greater capacity and flexibility in operating a digitalcomputer. In particular, the developments in integrated circuits haveprovided for increased memory capacity and different types of memorydevices. One such memory device is the Double Data Rate Dynamic RandomAccess Memory, referred to as DDR DRAM.

DDR DRAM transfers data at both the rising and falling edge of a clocksignal, unlike traditional SDRAM, which transfers data only on therising edge of a clock signal. In operation, DDR and similar memorydevices utilize differential signaling for clock signals at clock pinsof a device package. Differential signaling for these clock signalsreduces sensitivity to common mode voltages to enable the production ofa stable internal timing reference. Typically, a differential signalprovides good signal integrity from which a balanced receiver can bebuilt that maintains good duty cycle performance internally. However,DDR and similar memory devices utilize non-differential signaling fordata signals input on the device data pins. The received data signalsare compared to a voltage reference voltage supplied by the system. Thelack of differential signaling for the received data signals introducessensitivities to both the common mode signal voltage and referencevoltage levels. As a result, the received data signals exhibit timingskew relative to the received clock signals, when the signaling levelsdepart from ideal.

The non-differential signals and their sensitivity to the system voltagereference, VREF, may result in data signal offsets, which requires somecompromise in building the receivers used in applications such as memorydevices. As a result of these design compromises, the internal signalsafter capture generally do not have the same duty cycle integrity as thesystem clock signal. This reduction in duty cycle integrity could be dueto several reasons. Imbalances in the memory buffers can occur duringwafer processing due to variations between p-type channel devices andn-type channel devices in drive strength that can vary from wafer towafer. Invariably, the p to n drive strength ratios are not as balancedas initially designed. This variation from the design is a factor whenexamining the received data signal relative to VREF.

The data signal is examined relative to a trip point of a data receiver.A trip point is essentially the transition point, or transitionthreshold, at which the data receiver transitions from a one to a zero,that is, the point at which, when the input changes from one level toanother, the output changes from one level to another. Ideally, the trippoint should be exactly equal to VREF. As the received data signaltransitions through the voltage level represented by VREF, the output ofthe receiver will transition from one state to another. Thus, the datasignals are being examined relative to the VREF level in the circuitryof the data receivers using p-type and n-type device elements. Withimbalances from the design in the p to n drive strength ratio, the trippoint may be somewhat shifted from VREF. As a result, imbalances in aduty cycle may occur, or the rise and fall times of the data signal andthat of a data buffer may not be matched as desired. As a result, sometiming skews relative to the received clock signal may occur. Then,generally, as data is sent from the data receivers to data latches, anykind of timing skew incurred in the data receivers translates intoset-up and hold timing problems.

Generally, VREF is a reference voltage set as one-half the power supply.If data signals swing from VSS to VDD, VREF should be (VDD−VSS)/2. Theideal level for VREF is to be perfectly centered in the signal swing. IfVREF is not centered in the signal swing, the output duty cycle from thedata receiver can be affected. Further, any noise on the VREF input tothe receiver could potentially affect the timing of the output signal ina high speed device. In a high speed device, the design intent is toguarantee certain set up and hold times, such that measured from wherethe clock makes a transition, there is a certain set up time requirementwhere data has to be transitioned and settled before the clocktransition occurs. At higher frequencies, the set up and hold time issmaller, thus any errors or deviations from design created on the chipdie will negatively affect set up and hold times. In addition to makingintegrated circuits as accurate as possible, there is a need to correctfor imbalances in the transistors in the integrated circuit, and correctfor DC offsets in the VREF signal.

Typically, once the integrated circuit has been made, data signaloffsets and timing skews are not corrected during operation of theprocessed integrated circuit. A problem dealing with adjusting timingoffsets of a digital signal relative to a coincident clock signal hasbeen addressed in U.S. Pat. No. 6,029,250, entitled “Method andApparatus for Adaptively Adjusting the Timing Offset Between a ClockSignal and Digital Signals Transmitted Coincident with that ClockSignal, and Memory Device and System Using the Same,” and assigned tothe assignee of the present invention. In the above patent, a number ofdigital signals with respective timing offsets are stored and evaluated,where one of the timing offsets from the number of digital signalsstored is selected to be used to adjust the timing offsets for thedigital signals. Such an approach will not fully address the problemspreviously discussed. There remains a need for correcting data signalingoffsets and timing skews in a data receiver as it operates. The presentinvention provides a solution to this problem.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a memory device depicting elements of thememory device including a data corrector in accordance with the presentinvention.

FIG. 2 is a block diagram of a data receiver having a trip pointadjustor in accordance with the present invention.

FIG. 3 depicts a receiver portion of a data receiver without a trippoint adjustor.

FIG. 4 depicts an exemplary schematic of a data receiver having a trippoint adjustor in accordance with the present invention.

FIG. 5 is a block diagram depicting elements of the data corrector inaccordance with the present invention.

FIG. 6 depicts an exemplary schematic of a phase detector that providessignal balancing and detection of a zero crossing of signals inaccordance with the present invention.

FIG. 7 depicts a block diagram of a corrector controller for providingadjustment vectors in accordance with the present invention.

FIG. 8 depicts a block diagram of portions of the elements of a datacorrector used to adjust trip points of a set of data receivers.

FIG. 9 depicts timing diagrams for a data corrector operating withoutadjustment vector correction.

FIG. 10 depicts timing diagrams for a data receiver operating withadjustment vector correction in accordance with the present invention.

FIG. 11 depicts a processing system having memory devices in accordancewith the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings which form a part hereof,and in which is shown by way of illustration specific preferredembodiments in which the invention may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention, and it is to be understood that otherembodiments may be utilized and that logical, mechanical and electricalchanges may be made without departing from the spirit and scope of thepresent inventions. The following detailed description is, therefore,not to be taken in a limiting sense, and the scope of the presentinvention is defined only by the appended claims and their equivalents.

The term, VCC, refers to a supply voltage that is used to provideoperating voltages for the electronic elements used in accordance withthe present invention. The terms, VDD and VSS, refer to voltagessupplying the necessary voltages to a drain and a source, respectively,for n-type and p-type FETs and MOS transistors needed for operation ofthese transistors. For a particular transistor, its VDD and/or VSS isVCC reduced by a voltage drop across some load, as should be understoodby those skilled in the art.

In accordance with embodiments of the present invention, an electronicdevice includes a data corrector that provides adjustment informationfor adjusting the trip point of data receivers included in theelectronic device. For offsets in the trip point from a referencevoltage, VREF, the data corrector provides adjustment signals that shiftthe trip point of the data receivers in the electronic device relativeto VREF. The data corrector uses differential clock signals, and VREF togenerate the set of adjustment signals.

In another embodiment of the present invention, a data receiver includesa receiver having a trip point, and a trip point adjustor. The trippoint adjustor uses received adjustment vectors to provide signals tothe receiver for adjusting the receiver's trip point.

In another embodiment of the present invention, a data correctorincludes a pair of ancillary data receivers and a corrector controllerthat provides the ancillary data receivers with adjustment vectors. Thecorrector controller also supplies adjustment vectors to data receiversexternal to the data corrector. A voltage reference, VREF, is coupled tothe ancillary data receivers, along with coupling differential clocksignals at the data ports to the ancillary data receivers. The outputsignals of the ancillary data receivers are compared by a phase detectorto determine if they cross concurrently at a zero point for a signaltransition (high to low or low to high). If these output signals do notcross concurrently, adjustment vectors are generated and coupled to theancillary data receivers to adjust their trip point relative to (VCC/2).Adjustment vectors are continually supplied to the two ancillary datareceivers, adjusting their trip point until their output signals crossconcurrently. The adjustment vectors that result in the output signalsfrom the ancillary data receivers crossing concurrently are selected asthe adjustment vectors that the corrector controller supplies to datareceivers external to the data corrector.

In another embodiment of the present invention, a phase detectorincludes circuitry for balancing two signals and comparing a zerocrossing of the two signals. The phase detector compares the rising edgeof one clock signal with the falling edge of the other clock signal.

In another embodiment of the present invention, a processing systemincludes a central processing unit, and a plurality of memory deviceshaving a data corrector for supplying adjustment vectors to the datareceivers included in each memory device. The memory device receivesdifferential system clocks, and a voltage reference, VREF, to generatethe adjustment vectors for the data receivers in the memory devices.

In another embodiment of the present invention, a method of operating adata corrector includes providing two clock signals to a pair ofancillary data receivers, determining a difference between the outputsignals of the ancillary data receivers, and generating adjustmentvectors correlated to the difference in the output signals of theancillary data receivers. One clock signal is coupled to the data portof one ancillary data receiver, and the other clock signal is coupled tothe data port of the other ancillary data receiver.

FIG. 1 shows a block diagram of a portion of a memory device 100depicting elements of memory device 100 including a data corrector 101in accordance with the present invention. Data signals are received bymemory device 100 at data ports 114 a-114 n. The data signals at thesedata ports are coupled to data receivers 102 a-102 n for furtherprocessing. Typically, these data ports may be data pins on anintegrated circuit. The data signals may include data to be stored inmemory array 107, commands, or address signals. Various other systemsignals are received by memory device 100 at a system signals port 113for operating memory device 100 in conjunction with external systems.System signals port 113 provides system signals to internal signals unit115 used to generate internal system signals for operating memory device100 including a BIAS signal, an enable signal EN, a RESET signal, andVCC.

Transferring data throughout a memory device is accomplished inconjunction with stable timing signals. For instance, as data isdistributed from data receivers to other functional sections of memorydevice 100, it is first clocked into data latches such as data latches105, 106. Data latches 105, 106 and other data latches receive clocksignals to move data in and out of the latches. Two stable clocksignals, CLKOUT0 and CLKOUT1, are provided by the internal clock unit109 for internal use in memory device 100. However, the clock signals,CLKOUT0 and CLKOUT1, from internal clock unit 109 are generated fromdifferential clock signals that memory device 100 receives from anexternal system, typically from a unit on a motherboard of a system towhich the memory device is coupled. The differential system clocksignals, CLKIN0 and CLKIN1, are received at a CLKIN0 port 110 and aCLKIN1 port 111, respectively, and coupled to the internal clock unit109. The differential system clock signals are also used to generateadjustment vectors by data corrector 101 for adjusting the trip pointsof the data receivers 102 a-102 n. In addition to being coupled to theCLKIN0 port 110 and the CLKIN1 port 111 to receive the differentialsystem clock signals, data corrector 101 is coupled to a VREF port 112for receiving a system reference voltage, VREF, that forms a basis forthe operation of data corrector 101.

The main function of data corrector 101 is to generate adjustmentvectors that are used internal to data corrector 101 in a feedbackmanner, and are supplied to data receivers external to data corrector101, once operating parameters within data corrector 101 are meet. Theadjustment vectors are 8 bit vectors configured in two 4 bit pairs. Theadjustment vectors that are supplied externally by data corrector 101are held in an adjustment vector latch 108 that is coupled via 8 linesbetween data corrector 101 and the data receivers 102 a-102 n. Thecontrol logic for sending adjustment vectors to the data receivers ismaintained within data corrector 101. Alternately, adjustment vectorlatch 108 can be incorporated into data corrector 101.

In determining the adjustment vectors, the received differential clocksignals, CLKIN0 and CLKIN1, are used to determine the corrections to bemade in the data receivers 102 a-102 n. CLKIN0 and CLKIN1 are freerunning clock signals, that is, continuously cycling signals withdefinite transitions. Data corrector 101 examines CLKIN0 and CLKIN1relative to VREF. Using CLKIN0 and CLKIN1 as data signals, datacorrector 101 determines adjustment information for adjusting dataoffsets, not to adjust for VREF, but to adjust or modify trip points ofdata receivers. Once data corrector 101 has determined, within datacorrector 101, the amount of adjustment needed to adjust a trip pointtowards (VCC/2), which is ideally set at the 50% point of a data signal,it provides information signals to adjust the trip points of datareceivers 101 a-n. The detailed description of data corrector 101 andits functional units will be provided in further discussions to follow.

It should be understood by those skilled in the art that the elements ofthe block diagram of FIG. 1 are some of the functional elements of amemory device, and not all elements of a memory device are depicted.FIG. 1 includes those functional elements that are necessary to practicethe present invention. In one embodiment of the present invention, thememory device 100 is an integrated circuit wherein the ports representedas 110-114 a-n are pins of the integrated circuit. In anotherembodiment, memory device 100 is a die wherein the ports represented as110-114 a-n are the contact pads formed in the die, and the functionalunits of the memory device are fabricated in the die using standardfabrication methods as is known to those skilled in the art.

Advantageously, in accordance with the present invention, it isanticipated that the functioning of memory buffers within a memorydevice will be enhanced. Adaptively adjusting the trip point of datareceivers to correct for offsets and timing skews in a data signal willextend the range and timing accuracy of input buffers of the memorydevice that use these data receivers.

FIG. 2 depicts a block diagram for a data receiver 102 including areceiver 202 and a trip point adjustor 203. Receiver 202 has a trippoint, which is a reference level, or transition point, such that as theinput changes from one level to another, the output changes from onelevel to another. The trip point is essentially that transition pointfor judging an input as high or low, depending on the type logic used.Ideally, the trip point is set at the level of (VCC/2).

The structural details of data receiver 102 are used for fabricating thedata receivers 102 a-102 n of FIG. 1. Data is received by receiver 202from one of the data ports 114 a-114 n of memory device 100 of FIG. 1.Receiver 202 provides a DATAOUT signal to a latch, such as latch 105 ofFIG. 1. If there is no offset in the data in receiver 202, the DATAOUTsignal will essentially be the data into receiver 202. The function oftrip point adjustor 203 is to compensate receiver 202 to eliminate orreduce any offsets to the data. Trip point adjustor 203 receivesadjustment vectors from data corrector 101 of FIG. 1. Trip pointadjustor 203 is coupled to receiver 202 to apply the signals of thereceived adjustment vectors to receiver 202. Applying the signals of thereceived adjustment vectors pulls the trip point level down or pulls thetrip level up based on the adjustment vectors that the trip pointadjustor receives. Essentially, the signals of the adjustment vectorsturn on a set of transistors in trip point adjustor 203 that modifies abiasing voltage in receiver 202 by increasing or decreasing the biasingvoltage.

In data receiver 102, the design for receiver 202 can be a standardreceiver known to those skilled in the art. Based on the design ofreceiver 202, trip point adjustor 203 would be of a design that wouldallow the coupling of trip point adjustor 203 with receiver 202, whichwould result in modifying the trip point of receiver 202 based on theadjustment vectors received by the trip point adjustor. Thus, the designof the trip point adjustor would be dependent upon the topology ofreceiver 202 used in forming data receiver 102. A differential pairreceiver can be used as receiver 202. In an embodiment for a datareceiver 102, a modified Bazes receiver is used as is discussed in thefollowing detailed description of data receiver 102.

The term Bazes receiver is used to describe a receiver using the basictopology as disclosed by M. Bazes, IEEE Journal of Solid-State Circuits,vol. 26: no. 2, pp. 165-168 (1991). This receiver could also be referredto as a self-biased receiver. The Bazes receiver does not have a meansfor adjusting its trip point.

FIG. 3 depicts a receiver 202 that does not have a trip point adjustor,which is a portion of receiver 102 of FIG. 2. Receiver 202 utilizes thebasic elements of a self-biased amplifier discussed in theaforementioned article. It uses two input signals, a DATA signalreceived from a data port such as data port 114 of FIG. 1, and VREFreceived from VREF port 112 of FIG. 1. The EN signal is an enable signalthat essentially turns the receiver to an active state. It is one of thegroup of signals provided from internal signals unit 115 of FIG. 1. TheBIAS signal is also provided within the group of signals from internalsignals unit 115 of FIG. 1. The BIAS signal is a DC voltage levelapplied to the gate of the p-type MOS transistor 210 and to the gate ofthe n-type MOS transistor 212. BIAS is set at the low logic levelturning p-type MOS transistor 210 on and n-type MOS transistor 212 off.With receiver 202 enabled, the BIAS level is set such that the p-typeMOS transistor 210 is continuously on providing a bias load, and thegrounding transistor 212 is off. When the receiver is to be turned off,the BIAS level is set to the high logic level turning off transistor 210and turning on transistor 212 to ground the signal at an output node271. The BIAS signal and EN signal are operated together to turn-offreceiver 202.

The basic elements for a Bazes receiver used for receiver 202 are p-typeMOS transistors 211,214 and 216, and n-type MOS transistors 213, 215,and 217, which are used in conjunction with NAND 246 and inverters 243,and 244 to provide DATAOUT with the proper polarity. The p-type MOStransistor 210 is used when turning off receiver 202, as is n-type MOStransistor 212, which is used to ground the output at node 271.

As mentioned, the Bazes receiver is basically a self-biasingdifferential amplifier. The DATA signal is applied to the gates of thetransistors 216 and 217, where transistors 216 and 217 form inverter 255with an output at node 271. The VREF signal is applied to the coupledgates of transistors 214 and 215, where transistors 214 and 215 forminverter 256 with an output at node 270. The output signal from inverter265 at node 270 is coupled to the gates of transistors 211 and 213. Thetransistors 211 and 213 are coupled to inverter 255. Thus, the output ofinverter 265 bias the inverter 255 by adjusting the VDD and VSS for thetransistor pair 216-217. With the inverter 255 coupled to the inverter265, feedback is provided to the inverter 265, whose output iscontrolled by the VREF signal, which in turn adjusts the bias toinverter 255, which is controlled by the DATA signal. An output is takenat node 271, where transistors 216 and 217 are coupled together, forfeeding data out receiver 102 through inverter 243, NAND gate 246, andinverter 244. The DATAOUT signal from 202 is the DATAOUT of datareceiver 102 to be coupled to a latch, such as data latch 105 of FIG. 1.

The trip point of receiver 202 is the trip point of inverter 255, whichis the input level at which its output transitions between low and high.The voltage at node 271 is controlled at the gates of inverter 255 byDATA, which as mentioned before is affected by the output at node 270 ofinverter 265 controlled by VREF. There is no means for controlling thevoltage at node 271 other than VREF and the DATA signal, which receiver202 does not control. Thus, receiver 202 does not have a means to adjustits trip point, other than varying VREF.

The transistors in receiver 202 can be fabricated using processes knownto those skilled in the art. In particular, p-type MOS transistor 214and n-type MOS transistor 215 are fabricated as a CMOS transistor, asare p-type MOS transistor 216 and n-type MOS transistor 217.

FIG. 4 depicts the basic elements for data receiver 102 including thecoupling of receiver 202, and trip point adjustor 203 referenced in FIG.2. The trip point adjustor, in an exemplary embodiment of the presentinvention, includes a set of eight p-type MOS transistors 220-227, and aset of eight n-type MOS transistors 230-237. The two sets of eighttransistors are coupled at node 270, which is also a node common totransistors 211, 213-215 of receiver 202. Thus, driving the transistorsof the trip point adjustor with signals received externally from datareceiver 102, the voltage at node 270 of receiver 202 can be pulled upor pulled down affecting the trip point of data receiver 102.

The set of p-type MOS transistors, 220-227, of the trip point adjustorare coupled between node 270 and VCC. This set of eight transistors isconfigured as four transistor pairs in parallel, where the transistorsin each transistor pair are coupled together in series. One of the twotransistors acts as a switch transistor. The second of the twotransistors is used as a load. These transistor pairs are designed toraise the voltage level at node 270 by an offset. Those skilled in theart will readily recognize that a resistor or other load circuit couldbe used in place of the second transistor. Raising the voltage level atnode 270 by an offset lowers the trip point defined by inverter 255 ofthe receiver. The switch transistors 221, 223, 225, and 227 are coupledto a SKEWD port 260. The SKEWD port 260 comprises four inputs forreceiving a 4-bit SKEWD vector <0:3>. Each input is coupled to the gateof one of the four switch transistors in a one to one manner such thatone component of the SKEWD vector is applied to each transistor pair.For instance, SKEWD <0> is applied to the gate of 221 in the 220-221pair. The SKEWD vector is a set of adjustment signals supplying voltagelevels for controlling the set of transistors 220-227.

The set of n-type MOS transistors, 230-237, of the trip point adjustorare coupled between node 270 and ground. This set of eight transistorsis configured as four transistor pairs in parallel, where thetransistors in each transistor pair are coupled together in series. Oneof the two transistors acts as a switch transistor. The second of thetwo transistors is used as a load. These transistor pairs are designedto lower the voltage level at node 270 by an offset. Those skilled inthe art will readily recognize that a resistor or other load circuitcould be used in place of the second transistor. Lowering the voltagelevel at node 270 by an offset raises the trip point defined by inverter255 of the receiver. The switch transistors 231, 233, 235, and 237 arecoupled to a SKEWU port 261. The SKEWU port 261 comprises four inputsfor receiving a 4-bit SKEWU vector <0:3>. Each input of SKEWU port 261is coupled to the gate of one of the four switch transistors in a one toone manner such that one component of the SKEWU vector is applied toeach transistor pair. For instance, SKEWU <0> is applied to the gate of231 in the 230-231 pair. The SKEWU vector is a set of adjustment signalssupplying voltage levels for controlling the set of transistors 230-237.

Each transistor pair is designed to apply a different amount of offsetcalled a weighted offset. The weighting factor is determined by theratio of a width, W, of the transistor to a transistor length, L, wherethe ratio is related to the resistance of the transistor, when thetransistor is on. The resistance for each transistor pair is the sum ofthe resistance of the switching transistor and the load transistor. Thefour pairs of transistors, both for the set of p-type MOS transistorsand for the set of n-type MOS transistors, act as four resistors inparallel, where the resistance of a pair that is turned off acts as aninfinite resistance, and has no effect on the pull up or pull down ofnode 270, which lowers or raises, respectively, the trip point.

For the set of four pairs of p-type MOS transistors, the switchtransistors 221, 223, 225, 227 have the same resistance, i.e., the sameW/L ratio (20.0/1.0). The load transistors 220, 222, 224, 226 have adifferent relative weighting with respect to their length, L, whilehaving the same width, W. The relative width, W, for the loadtransistors is set at 20.0. The relative lengths of the load transistorsare 4.0 for load transistor 226, 8.0 for load transistor 224, 16.0 forload transistor 222, and 32.0 for load transistor 220. With such aweighting pattern, the weighting can be considered as a binaryweighting. These relative lengths are scaled to actual dimensionsdependent upon the shrinkage factor of the manufacturing process. Theabove relative dimensions were calculated for a process where W was setto 2.0 μm, and the lengths of the load transistors are 0.4 μm for loadtransistor 226, 0.8 μm for load transistor 224, 1.6 μm for loadtransistor 222, and 3.2 μm for load transistor 220. By turning onvarious combinations of p-type MOS transistor pairs, changes in theeffective resistive of the set of p-type MOS transistors between node270 and voltage supply VCC can be implemented. With the set of p-typeMOS transistors turned off, the voltage level at node 270 is set byreceiver 202 of FIG. 3. With one or more of the set of p-type MOStransistors on, the voltage at node 270 is raised by an offset dependingon the combination of p-type MOS transistors turned on, lowering thetrip point. With only transistor pair 220-221 on, the voltage at node270 is raised in offset for a VCC of 1.8V. The offset, raising thevoltage of node 270, pulls up node 270 resulting in a lowering of thetrip point defined by inverter 255 by about 10 mV. Thus, this offset dueto the set of p-type MOS transistors being on is a pull down of the trippoint. The pull down offset provided from the set of p-type MOStransistors ranges from 0 to about 200 mV. The 0 mV offset occurs forthe set of p-type MOS transistors turned off, which occurs when thegates of the switch transistors 221, 223, 225, 227 are set to a highlevel by a SKEWD vector <1,1,1,1>.

For the above discussion, the set of n-type MOS transistors also coupledat node 270 have not been considered. The adjustments provided to then-type and p-type MOS transistors are only applied to one set. If thep-type MOS transistors are on, then the n-type transistors will be off,and vice-versa. Both sets can be turned on, but this would result inexcessive current.

The weighting factors for the set of n-type MOS transistor are differentthan the p-type MOS transistors, since the drive strength is differentfor a n-type MOS transistors relative to a p-type MOS transistor. Forthe set of four pairs of n-type MOS transistors, the switch transistors231, 233, 235, 237 have the same resistance, i.e., the same W/L ratio(1.2/0.2). The load transistors 230, 232, 234, 236 have a differentrelative weighting with respect to their length, L, while having thesame width, W. The relative width, W, for the load transistors is set at12.0. The relative lengths of the load transistors are 4.0 for loadtransistor 236, 8.0 for load transistor 234, 16.0 for load transistor232, and 32.0 for load transistor 230. With such a weighting pattern,the weighting can be considered as a binary weighting. These relativelengths are scaled to actual dimensions dependent upon the shrinkagefactor of the manufacturing process. The above relative dimensions werecalculated for a process where W was set to 1.2 μm, and the lengths ofthe load transistors are 0.5 μm for load transistor 226, 0.9 μm for loadtransistor 224, 1.3 μm for load transistor 222, and 3.1 μm for loadtransistor 220. By turning on various combinations of n-type MOStransistor pairs, changes in the effective resistive of the set ofn-type MOS transistors between node 270 and ground can be implemented.With the set of n-type MOS transistors turned off, the voltage level atnode 270 is set by receiver 202 of FIG. 3. With one of more of the setof n-type MOS transistors on, the voltage at node 270 is lowered by anoffset depending on the combination of n-type MOS transistors turned on.With only transistor pair 230-231 on, the voltage at node 270 is loweredin offset for a VCC of 1.8V. This offset, lowering the voltage of node270, pulls down node 270, which raises the trip point of inverter 255 byabout 10 mV. Thus, this offset due to the activated set of n-type MOStransistors is a pull up of the trip point. The pull up offset providedfrom the set of n-type MOS transistors ranges from 0 to about 200 mV.The 0 mV offset occurs for the set of n-type MOS transistors turned off,which occurs when the gates of the switch transistors 221, 223, 225, 227are set to a low level by a SKEWU vector <0,0,0,0>.

For the above discussion regarding the set of n-type MOS transistors,the set of p-type MOS transistors also coupled at node 270 have not beenconsidered. Further, it is understood that a low vector <0,0,0,0>corresponds to a set of low voltages for turning a set of n-type MOStransistors off, while a high vector <1,1,1,1> corresponds to a set ofhigh voltages for turning a set of p-type MOS transistors off. Further,the SKEWD vector and the SKEWU vector are input to receiver 102, suchthat when one vector activates at least one transistor pair in the setof transistors to which it is coupled, the other vector turns off allthe transistors to which its signal is being applied.

The SKEWD and SKEWU vectors supply signals to drive the switchtransistors of the p-type MOS transistor pairs and the n-type MOStransistor pairs, respectively. This activates one or the other of thetwo sets of transistors in a set pattern adjusting the voltage at thenode 270. Trip point adjustor 203 of FIG. 2 is continually provided skewadjustments for receiver 202 of FIG. 2, based on the received adjustmentvectors. If data receiver 102 of FIG. 4 is operating at or approximatelyat (VCC/2) at startup, the adjustment vectors being supplied should besuch that the two set of skew transistors are not providing any pull upor pull down, that is, adjustment vector SKEWD has the voltage levelsfor a vector <1,1,1,1>, and adjustment vector SKEWU has the voltagelevels for a vector <0,0,0,0>.

The weighting factors for the two sets of eight skew transistors of FIG.4 are chosen so that an approximate range of ±200 millivolts of trippoint adjustment can be applied. Two sets of four transistor pairs, eachtransistor pair having a gate controlled by one of the components of theSKEWD and SKEWU adjustment vectors, are used to provide this offset.However, the number of transistor pairs in each set, which is also thenumber for the components of a corresponding adjustment vector, canrange from one to a number appropriate for a particular application.Increasing the number of transistor pairs in a set increases thegranularity of the offset for adjusting the trip point of the receiver.Associated with the increase number of skew transistors is an increasein the amount of the die used for fabricating a data receiver to includesuch a trip point adjustor. The weighting factors, number of componentsfor the adjustment vectors, and other feature characteristics for thecomponents of a data receiver can be determined in accordance with thepresent invention using standard simulation methods, as is known tothose skilled in the art.

In memory device 100 of FIG. 1, all data receivers are made inaccordance with the present invention as described for data receiver 102above. In addition, data corrector 101 includes a pair of ancillary datareceivers 301, 302, as shown in FIG. 5, that are essentially identicalto the data receivers 102 a-102 n of memory device 100. In FIG. 5, theuse of the ancillary data receivers 301, 302 will be discussed in thedetailed description of data corrector 101 provided below.

FIG. 5 depicts a data corrector 101 including a pair of ancillary datareceivers 301,302, and a corrector controller 305 coupled to eachancillary data receivers 301, 302 for providing adjustment vectors tothe trip points of the ancillary data receivers 301, 302. Ancillary datareceivers 301, 302 are data receivers in accordance with the presentinvention as described above. The data corrector 101 is used to correctoffsets and timing skews in a data signal. However, a data signal isnon-repetitive, making it a poor reference for data corrector 101.Advantageously, the data corrector uses received differential clocksignals in conjunction with VREF to provide adjustment vectors. Onereceived clock signal, CLKIN0, is coupled to ancillary data receiver 301at its data input, referred to as DATA in FIG. 2. The other receivedclock signal, CLKIN1, is coupled to ancillary data receiver 302 at itsdata input, referred to as DATA in FIG. 2. As shown in FIG. 5, bothancillary data receivers 301, 302 are coupled to the reference voltage,VREF. The outputs, CLK0 and CLK1, of the two ancillary data receivers301, 302, respectively, are coupled to phase detector 303. Phasedetector 303 is enabled along with the ancillary data receivers by an ENsignal. Phase detector 303 examines a crossing point of the two outputsignals, CLK0 and CLK1. If CLK0 and CLK1 do not cross concurrently at asignal transition from high to low for one signal, and low to high forthe other signal, phase detector 303 generates an UP pulse or a DOWNpulse, depending upon which signal has a transition arriving at phasedetector 303 first. Two lines, one for an UP pulse and one for a DOWNpulse, couple the output of phase detector 303 to a filter 304. In asample time frame, the phase detector puts either a pulse on the UPpulse line or on the DOWN pulse line.

Filter 304 is a majority filter, which is a loop filter that does notmake any changes, or corrections, until it receives a number of sampleUP pulses or a number of sample DOWN pulses. The higher the samplenumber, the more noise is filtered out with an accompanying slow down ofthe loop. With a high number of samples, a slowed loop reduces theability of data corrector 101 to track a fast variation about VREF,since the variations will have occurred before the filter allows a pulseto reach corrector controller 305. With a small number of samples thefilter can follow faster transitions, but then the filter may overcorrect. If the loop filter is set too fast (too few samples), the loopmay be unstable. The sample for filter 304 is four pulses. Alternately,the sample can be eight pulses. In addition to providing the UP pulseand the DOWN pulse to the corrector controller 305, filter 304 alsoprovides a clock signal, CNTRLCLK, for use by corrector controller 305.The CNTRLCLK is generated from the CLK0 and CLK1 from the ancillary datareceivers 301,302. Filter 304 can be set to an initial condition using aRESET signal to zero the count of filter 304.

The UP and DOWN pulses from phase detector 303 are coupled to correctorcontroller 305 having passed the sample requirement of filter 304. An UPpulse to corrector controller 305 is a request for a skew up, or pullup, of the trip point of the ancillary data receivers 301, 302.Similarly, a DOWN pulse to corrector controller 305 is a request for askew down, or pull down, of the trip point of the ancillary datareceivers 301, 302. Corrector controller 305 counts the UP and DOWNpulses from filter 304 using a control clock signal, CNTRLCLK, providedby filter 304. Based on its count, corrector controller 305 providesadjustment vectors, SKEWU<0:3> and SKEWD<0:3>, that are coupled backedto ancillary data receivers 301, 302.

Once the adjustment vectors are coupled back to the ancillary datareceivers 301, 302, the trip points of the ancillary data receivers 301,302 are adjusted with their outputs modified relative to each other. Themodified outputs, CLK0 and CLK1, are again compared by phase detector303. Phase detector 303 provides a new UP or DOWN request, and correctorcontroller 305 supplies a new set of adjustment vectors to the ancillarydata receivers 301, 302. This cycle continues until phase detector 303determines that no further adjustments are necessary, that is, CLK0 andCLK1 voltage levels cross concurrently at the transition of the risingedge of one signal and the transition of the falling edge of the othersignal. In practice the crossing is not perfectly at VCC/2, and thecycle continues. Additional complexity could be implemented such thatwhen the crossing occurs within a predetermined delta of VCC/2,corrector controller 305 can send the same set of adjustment vectors tothe ancillary data receivers 301, 302, which maintains the status oftheir trip points that resulted in the phase detector no longerrequesting a UP pulse or a DOWN pulse. Also when this condition occurs,corrector controller 305 outputs the adjustment vectors at a port 306for use by data receivers external to data corrector 101.

Phase detector 303 of FIG. 5 is shown in more detail in FIG. 6. FIG. 6depicts phase detector 303 having elements for balancing differentialclock signals and for detecting a zero crossing of the balanceddifferential clock signals. Two signals are balanced when correspondingcharacteristics of the two signals have the same or equivalent values orranges, such as signal voltage swings or duty cycles. Two clock signalscan also be balanced by adjusting the two signals so that the rise andfall times of the two clock signals are approximately equal. A zerocrossing for two signals having defined transitions from a low to a highcorresponds to the two signals crossing at the transition point from alow to a high (a high to a low) of each signal at the same time. A zerocrossing also occurs when the low to high transition in a rising edge ofone signal occurs at the same time as the high to low transition in afalling edge of the second signal.

In FIG. 6, phase detector 303 receives an output clock signal, CLK0,from ancillary data receiver 301, and an output clock signal, CLK1, fromancillary data receiver 302, as shown in FIG. 5. Phase Detector 303 thenbalances the rise and fall times of these two clock signals as theypropagate through phase detector 303. The balanced clock signals arecompared to determine a zero crossing of the two signals. The zerocrossing in this instance occurs when the transition of a rising edge ofone clock signal occurs concurrently with the transition of the fallingedge of the other clock signal. If the two clock signals do not have azero crossing, then the transitions for one clock signal will lead thetransitions for the other clock signal. Phase detector 303 at its outputplaces a pulse on the UP output if a transition occurs first in the CLK0signal, and places a pulse on the DOWN output if a transition occursfirst in the CLK1 signal.

The balancing of the two clock signals is performed using the two NANDgates 310, 311, inverters 314, 315, and capacitors 316-320. Thecapacitors 316-319 are n-type capacitors, each fabricated as a n-typetransistor with its source and drain connected, while 320 is a p-typecapacitor fabricated as a p-type transistor with its source and drainconnected. These capacitors could be fabricated in other ways as isknown to those skilled in the art. The amount of n-type capacitance andp-type capacitance at a given node are determined by matching n-typecapacitance and p-type capacitance at the given node including the inputgate capacitance with the result that the rise and fall times of the twosignals, CLK0 and CLK1, match as they propagate through the circuit.Through simulation of the circuit depicted in FIG. 6, the drivestrengths for the circuit elements can be determined. Standard methodsof simulation can be used that are known to those skilled in the art.

Typically, phase detectors compare either a rising edge of a signal to arising edge of another signal, or a falling edge of a signal to afalling edge of another signal. Significantly, phase detector 303 inaccordance with the present invention, compares a rising edge of a clocksignal to a falling edge of another clock signal. This comparison isperformed using a NAND gate 312 and a NOR gate 313 with CLK0 coupledthrough the balancing circuit of phase detector 303 to the NAND gate312, and CLK1 coupled through the balancing circuit to the NOR gate 313.Further, the output of the NAND gate 312 is coupled though inverter 330to the input of the NOR gate 313, while, similarly, the output of theNOR gate 313 is coupled through inverter 331 to the input of NAND gate312. The output of NAND gate 312 is coupled through inverters 332, 333to a transmission gate formed by transistors 335-338. The output of NORgate 313 is coupled through inverter 334 to a transmission gate formedby transistors 335-338. Transistors 335, 337 are p-type MOS transistors,while transistors 336, 338 are n-type MOS transistors. The result, fromdetermining whether a zero crossing of the two signals CLK0 and CLK1 hasoccurred, is coupled out through inverters 340-341 and inverters342-343.

Phase detector 303 has two outputs, UP and DOWN. With a pulse (a highsignal) on either UP or DOWN, the phase detector has determined that thetransitions in the rising edge and the falling edge of the two signalsCLK0 and CLK1 have not crossed concurrently. The high signal will be setaccording to whichever of the two signals CLK0 and CLK1 makes its signaltransition first. With phase detector 303 used in data corrector 101 asdepicted in FIG. 5, a high for the UP output is a request for a shiftup, while a high for the DOWN output is a request for a shift down. Therequests are provided to corrector controller 305, which uses therequest to generate adjustment vectors.

FIG. 7 is a block diagram of the basic elements of corrector controller305. Inputs to corrector controller 305 include a request, UP, forpulling up the trip point of the ancillary data receivers 301, 302 ofFIG. 5, and a request, DOWN, for pulling down the trip point of theancillary data receivers 301, 302. Corrector controller 305 counts therequests in an UP counter circuit 501 and a DOWN counter circuit 502,using a CNTRLCLK clock signal to clock the counters in the UP countercircuit 501 and the DOWN counter circuit 502. Each time a UP or DOWNrequest occurs, the UP counter circuit 501 or the DOWN counter circuit502 increase their count accordingly. Only one counter counts at a time.A LOCKOUT is provided between the UP counter circuit 501 and the DOWNcounter circuit 502, sot that only one counts. Both counter circuits501, 502 include four counters which provide the outputs of correctorcontroller 305 as determined by control logic 510. The four counters ofthe UP counter circuit 501 provide the 4-bit SKEWU <0:3> vector atoutput 508. The four counters of the DOWN counter circuit 502 providethe 4-bit SKEWD <0:3> vector at output 509.

When data corrector 101 of FIG. 5 is first powered up, data corrector101 starts in a condition such that the outputs of the counter circuit501, 502 provide no offset adjustment to the ancillary data receivers301, 302 of FIG. 5. The signal that places data corrector 101 into thisinitial condition is provided by the RESET input. In the initialcondition, the RESET signal sets the counters of the counter circuits501, 502 to zero. This zeroing of the counters results in the signals inthe SKEWU vector being all low, and the signals in the SKEWD vectorbeing all high. Subsequently, unless the ancillary data receivers 301,302 are operating without any data offsets with respect to (VCC/2),phase detector 303 of FIG. 5 will determine a request for a shift UP ora shift DOWN of the trip points of the ancillary data receives 301, 302.Assuming an UP request is received by corrector controller 305, therequest will cause the UP counter circuit 501 to increase its count.Corrector controller 305 will generate adjustment vectors that reflectthe UP request. The resulting vector SKEWU at output 508 and the SKEWDvector at output 509 reflect that the adjustment is skewed from theprevious correction cycle, or adjustment cycle, towards pulling up thetrip point of the ancillary data receivers 301, 302.

When the trip point is so adjusted, the duty cycle of the differentialclock signals, CLKIN0 and CLKIN1, (input as data signals to theancillary data receivers 301, 302 of FIG. 5) is changed. The outputsignals of the ancillary data receivers, CLK0 and CLK1, are againcompared by phase detector 303 of FIG. 5. If the previous pull upadjustment is too much, corrector controller 305 receives a DOWNrequest, and if the previous pull up adjustment is not enough, correctorcontroller 305 receives a UP request. This cycle continues tracking anyoffsets in the ancillary data receivers 301, 302 until a zero crossingof CLK0 and CLK1 occurs. Once CLK0 and CLK1 transitions crossconcurrently, corrector controller 305 continues to supply the sameadjustment vectors according to the UP or DOWN request received. Theadaptive adjustment of the ancillary data receivers 301, 302 occurs indata corrector 101 in the configuration shown in FIG. 5. The datareceivers 102 a-102 n of FIG. 1 are not adjusted in the same manner asthe ancillary data receivers 301, 302. Corrector controller 305 suppliesadjustment vectors to the data receivers 102 a-102 n only when the datacorrect controller 305 in its control logic 510 has determined that theadjustment vectors require no additional, significant changes.

FIG. 8 depicts portions of the elements of data corrector 101 of FIG. 5in relation to the data receivers 102 a-102 n of FIG. 1 for operatingthe data corrector in accordance with the present invention. A method ofoperating a data corrector 101 includes providing differential clocksignals to a pair of ancillary data receivers 301,302, determining adifference between the output signals of the ancillary data receivers301, 302, and generating adjustment vectors correlated to the differencein the output signals of the ancillary data receivers. One differentialclock signal, CLKIN0, is coupled to the data port of ancillary datareceiver 301, and the other clock signal, CLKIN1, is coupled to the dataport of ancillary data receiver 302. The adjustment vectors generated incorrector controller 305 are coupled back to the pair of ancillary datareceivers 301, 302 to adjust the trip points of the ancillary datareceivers 301, 302.

Since the method uses continuously cycling clock signals, with definitetransitions, data corrector 101 is continually supplying the ancillarydata receivers 301, 302 with adjustment vectors. In practical terms,phase detector 303 will not detect a perfect zero crossing of the outputsignals, CLK0 and CLK1, from the ancillary data receivers 301, 302.Therefore, phase detector 303 continually provides an UP or DOWNrequest. The combination of the count in the filter 304 and the controllogic of the corrector controller 305 determines when that there is noappreciable offset in the ancillary data receivers 301, 302. The finalset of adjustment vectors determined to have provided the adjustment toancillary data receivers 301, 302 can be provided to data receivers 102a-102 n. The data receivers 102 a-102 n function in a system as datareceivers, as opposed to the ancillary data receivers 301, 302 of datacorrector 101, which receive clock signals as data for the process ofdetermining the set of adjustment vectors that will correct for datasignal offsets.

Data corrector 101 will maintain the final adjustment vectors in a latch108, and control the transfer of the adjustment vectors from the latchto data receivers external to the adjustment process, such as datareceivers 102 a-102 n. Data corrector 101 determines whether the datareceivers 102 a-102 n to receive the adjustment vectors are in a quietperiod. For example, a quiet period would constitute a time period inwhich system data is not being transferred into or out of the datareceivers. The adjustment vectors are transferred to the data receivers102 a-102 n to adjust their trip points during these quiet points toavoid any glitches that may be associated with changing a trip pointduring data processing.

As a system having data receivers operates, the data receivers, such asdata receivers 102 a-102 n, may experience periodic data offsets. Sincedata corrector 101 is continuously operating, new occurrences of dataoffsets, such as data offsets due to variations in VREF, will bedetected by data corrector 101, which will continue its process ofgenerating adjustment vectors. Data corrector 101 supplies a correctedadjustment vector from corrector controller 305 to the data receivers102 a-102 n, once data corrector 101 has determined that this correctedadjustment vector has adjusted for the offsets in the ancillary datareceivers 301, 302 of data corrector 101. In this manner, data corrector101 adaptively provides trip point adjustments to data receivers 102a-102 n to which it is coupled.

Data corrector 101, the ancillary data receivers 301, 302, and the datareceivers 102 a-102 n in this method of the present invention have beenpreviously described above. The data receivers 301, 302 and theancillary data receivers 102 a-102 n have the same design. The datareceivers 102 a-102 n and the ancillary data receivers 301, 302 differin use, where the data to the data receivers 102 a-102 n is an actualdata signal, while the data to each ancillary data receiver 301, 302 isa clock signal. This method in accordance with the present inventionallows commands and data to be received in data receivers that have beencorrected for any data offsets relative to VREF or any imbalances in thedata receivers themselves.

A method for operating an electronic device, data receiver, memorydevice, or other system that requires adjustments to correct for offsetsin a data signal has its best results when the data signal and the clocksignals used to generate adjustment signals are derived from the samesource. Typically, data signals and clock signals from a common sourcehave the same levels of voltage swing. Using clock signals as inputs toa data corrector circuit, the clock signals are expected to swingbetween the same voltage levels as the data signals swing in a datareceiving unit that is to be adjusted. Preferably, the data signal andclock signals come from the same chipset. However, the present inventionis not limited for use where clock signals and data have a commonsource.

The method in accordance with the present invention can be used forapplications involving a reference signal, either generated internallyor externally to an electronic device, associated with signalingconnected to a bus. Further, the adjustment vectors rather than digitalsignals (high, low voltage levels) could comprise analog controlvoltages for adjusting the trip point, or threshold transition, of anelectronic device. Obviously, noise problems associated withdistributing analog signals make the digital approach more advantageous.

In FIG. 9 shows timing diagrams for a data corrector operating withoutadjustment vector correction from a simulation of the operation anddesign of the data corrector in accordance with the present invention.One timing diagram depicts the system differential clock signals, CLKIN0901 and CLKIN1 902, which are coupled to data corrector 101 as shown inFIG. 5. CLKIN0 is coupled at the data input to ancillary data receiver301. CLKIN1 is coupled at the data input to ancillary data receiver 302.Both ancillary data receivers are coupled to VREF 903, which has avoltage level of 0.825 mV. CLKIN0 and CLKIN1 range from about 0.225 mVto about 1.025 mV. A second timing diagram shows the clock signals,CLKOUT1 904 and CLKOUT0 905, which are generated from CLKIN1 and CLKIN0in the internal clock unit 109 used in memory device 100 of FIG. 1.CLKOUT0 and CLKOUT1 range from about 0.0 mV to about 1.60 mV. The thirdtiming diagram shows the clock signal, CLK1 906, at the output ofancillary data receiver 302 having CLKIN1 as its data input. Also shownin the third timing diagram is the clock signal, CLK0 907, at the outputof ancillary data receiver 301 having CLKIN0 as its data input. CLK0 andCLK1 also range from about 0.0 mV to about 1.60 mV. With no appreciabledata offsets or timing skews, the CLK1/CLK0 pattern should resemble theCLKOUT1/CLKOUT0 pattern. The pattern shown in FIG. 9 indicates thepresence of data offsets and timing skews, as the outputs of theancillary data receivers 301, 302 cross at approximately 0 mV. TheCLK1/CLK0 pattern should cross near (VCC/2) 909.

FIG. 10 shows timing diagrams for a data corrector operating withadjustment vector correction from a simulation of the operation anddesign of the data corrector in accordance with the present invention.One timing diagram depicts the system differential clock signals, CLKIN0901 and CLKIN1 902, which are coupled to data corrector 101 as shown inFIG. 5. CLKIN0 is coupled at the data input to ancillary data receiver301. CLKIN1 is coupled at the data input to ancillary data receiver 302.CLKIN0 and CLKIN1 range from about 0.225 mV to about 1.025 mV. Bothancillary data receivers are coupled to VREF 903, which has a voltagelevel of 0.825 mV. A second timing diagram shows the clock signals,CLKOUT1 904 and CLKOUT0 905, which are generated from CLKIN1 and CLKIN0in the internal clock unit 109 used in memory device 100 of FIG. 1.CLKOUT0 and CLKOUT1 range from about 0.0 mV to about 1.60 mV. The thirdtiming diagram shows the clock signal, CLK1 1002, at the output ofancillary data receiver 302 having CLKIN1 as its data input. Also shownin the third timing diagram is the clock signal, CLK0 1001, at theoutput of ancillary data receiver 301 having CLKIN0 as its data input.CLK0 and CLK1 also range from about 0.0 mV to about 1.60 mV. With noappreciable data offsets or timing skews, the CLK1 /CLK0 pattern shouldresemble the CLKOUT1/CLKOUT0 pattern. The pattern shown indicates thatthe data corrector is adjusting the trip point of the ancillary datareceivers 301, 302, since the CLK1/CLK0 pattern crosses near (VCC/2)909. The crossing points do not occur at exactly the same level in eachtime frame, as the trip points are being adaptively adjusted overseveral cycles. However, the crossing point has been moved to near(VCC/2) 909.

FIG. 11 depicts a processing system 600 including, among other elements,a processor 601, a data bus 602, and set of memory devices100(a)-100(n), in accordance with the present invention. The processor601 and memory bus 602 are designed, made, and operated in accordancewith standard practices as known to those skilled in the art. The set ofmemory device 100(a)-100(n) are made and operated in accordance with thepresent invention. The memory devices 100(a)-100(n) have data receiverswith trip points adaptively adjusted to correct offsets and timing skewsin the data signals to these data receivers. The processing system 600may also include other memory devices that are not made or operated inthe same manner as memory devices 100(a)-100(n). Processor 601 may alsoinclude the present invention.

The illustrated embodiments may be changed, modified, and/or implementedusing various circuit types and arrangements. Those skilled in the artwill readily recognize that such modifications and changes may be madeto the present invention without strictly following the exemplaryembodiments and applications illustrated and described herein, andwithout departing from the true spirit and scope of the presentinvention which is set forth in the following claims.

1. An electronic apparatus comprising: a data receiver including: areceiver having a trip point; and a trip point adjustor coupled to thereceiver to adjust the trip point of the receiver.
 2. The electronicapparatus of claim 1, wherein the receiver includes: a first transistorpair having a first p-type MOS transistor coupled to a first n-type MOStransistor at a first node, a gate of the first p-type MOS transistorcoupled to a gate of the first n-type MOS transistor; a secondtransistor pair having a second p-type MOS transistor coupled to asecond n-type MOS transistor at a second node, a gate of the secondp-type MOS transistor coupled to a gate of the second n-type MOStransistor, the second p-type MOS transistor of the second transistorpair coupled to the first p-type MOS transistor of the first transistorpair at a third node, the second n-type MOS transistor of the secondtransistor pair coupled to the first n-type MOS transistor of the firsttransistor pair at a fourth node; a third p-type MOS transistor coupledto the third node; and a third n-type MOS transistor coupled between thefourth node and ground having a gate coupled to a gate of the thirdp-type MOS transistor at the first node.
 3. The electronic apparatus ofclaim 1, wherein the receiver includes a differential pair receiver. 4.The electronic apparatus of claim 1, wherein the receiver includes: adifferential amplifier; a voltage reference port coupled to an input ofthe differential amplifier; and a data port coupled to another input ofthe differential amplifier.
 5. The electronic apparatus of claim 4,wherein the trip point adjustor includes: a plurality of seriesconfigured n-type MOS transistor pairs coupled to a node of thedifferential amplifier; and a plurality of series configured p-type MOStransistor pairs coupled to the differential amplifier at the node,wherein activating the plurality of n-type MOS transistor pairs and theplurality of p-type MOS transistor pairs adjusts a voltage at the node.6. The electronic apparatus of claim 5, wherein the trip point adjustorincludes a plurality of adjustment ports configured in two sets, one setcoupled to the plurality of series configured n-type MOS transistorpairs in a one to one manner, the other set coupled to the plurality ofseries configured p-type MOS transistor pairs in a one to one manner,wherein the plurality of series configured n-type MOS transistor pairsand the plurality of series configured p-type MOS transistor pairs havean equal number of transistors, the two sets of adjustment portsconfigured to provide signals to activate the plurality of n-type MOStransistor pairs and the plurality of p-type MOS transistor pairs. 7.The electronic apparatus of claim 5, wherein the plurality of seriesconfigured n-type MOS transistor pairs is four, and the plurality ofseries configured p-type MOS transistor pairs is four.
 8. The electronicapparatus of claim 5, wherein the voltage at the node is adjusted in arange from about minus 200 mV to about positive 200 mV.
 9. Theelectronic apparatus of claim 5, wherein the plurality of seriesconfigured n-type MOS transistor pairs include a weighted set of seriesconfigured n-type MOS transistor pairs, and the plurality of seriesconfigured p-type MOS transistor pairs include a weighted set of seriesconfigured p-type MOS transistor pairs.
 10. The electronic apparatus ofclaim 9, wherein the weighted set of series configured n-type MOStransistor pairs and the weighted set of series configured p-type MOStransistor pairs are weighted based on a width to a length ratio foreach n-type MOS transistor acting as a load transistor in the seriesconfigured n-type MOS transistor pairs and for each p-type MOStransistor acting as a load transistor in the series configured p-typeMOS transistor pairs.
 11. The electronic apparatus of claim 1, whereinthe electronic apparatus includes a processor.
 12. An electronicapparatus comprising: a data receiver including a receiver having a trippoint and a trip point adjustor coupled to the receiver to adjust thetrip point of the receiver, the receiver and the trip point adjustorincluding: a first transistor pair having a first p-type MOS transistorcoupled to a first n-type MOS transistor at a first node, a gate of thefirst p-type MOS transistor coupled to a gate of the first n-type MOStransistor; a second transistor pair having a second p-type MOStransistor coupled to a second n-type MOS transistor at a second node, agate of the second p-type MOS transistor coupled to a gate of the secondn-type MOS transistor, the second p-type MOS transistor of the secondtransistor pair coupled to the first p-type MOS transistor of the firsttransistor pair at a third node, the second n-type MOS transistor of thesecond transistor pair coupled to the first n-type MOS transistor of thefirst transistor pair at a fourth node; a third p-type MOS transistorcoupled to the third node; a third n-type MOS transistor coupled betweenthe fourth node and ground having a gate coupled to a gate of the thirdp-type MOS transistor at the first node; a plurality of seriesconfigured n-type MOS transistor pairs coupled between the first nodeand ground; and a plurality of series configured p-type MOS transistorpairs coupled between a first voltage and the first node, whereinactivating the plurality of series configured n-type MOS transistorpairs and the plurality of series configured p-type MOS transistor pairsadjusts a voltage at the first node.
 13. The electronic apparatus ofclaim 12, wherein the plurality of series configured n-type MOStransistor pairs include a weighted set of series configured n-type MOStransistor pairs, and the plurality of series configured p-type MOStransistor pairs include a weighted set of series configured p-type MOStransistor pairs.
 14. The electronic apparatus of claim 13, wherein theweighted set of series configured n-type MOS transistor pairs and theweighted set of series configured p-type MOS transistor pairs areweighted based on a width to a length ratio for each n-type MOStransistor acting as a load transistor in the series configured n-typeMOS transistor pairs and for each p-type MOS transistor acting as a loadtransistor in the series configured p-type MOS transistor pairs.
 15. Anintegrated circuit comprising: a data receiver including a receiverhaving a trip point and a trip point adjustor coupled to the receiver toadjust the trip point of the receiver, the receiver and the trip pointadjustor including: a first transistor pair having a first p-type MOStransistor coupled to a first n-type MOS transistor at a first node, agate of the first p-type MOS transistor coupled to a gate of the firstn-type MOS transistor; a second transistor pair having a second p-typeMOS transistor coupled to a second n-type MOS transistor at a secondnode, a gate of the second p-type MOS transistor coupled to a gate ofthe second n-type MOS transistor, the second p-type MOS transistor ofthe second transistor pair coupled to the first p-type MOS transistor ofthe first transistor pair at a third node, the second n-type MOStransistor of the second transistor pair coupled to the first n-type MOStransistor of the first transistor pair at a fourth node; a third p-typeMOS transistor coupled to the third node; a third n-type MOS transistorcoupled between the fourth node and ground having a gate coupled to agate of the third p-type MOS transistor at the first node; a pluralityof series configured n-type MOS transistor pairs coupled between thefirst node and ground; and a plurality of series configured p-type MOStransistor pairs coupled between a first voltage and the first node,wherein activating the plurality of series configured n-type MOStransistor pairs and the plurality of series configured p-type MOStransistor pairs adjusts a voltage at the first node.
 16. The integratedcircuit of claim 15, the integrated circuit including: a voltagereference port coupled to the gate of the first p-type MOS transistor ofthe first transistor pair capable of providing a voltage referencesignal; and a data port coupled to the gate of the second p-type MOStransistor of the second transistor pair capable of providing a datasignal.
 17. An electronic apparatus comprising: a plurality of datareceivers, each data receiver having a receiver with a trip point andhaving a trip point adjustor; and a data corrector coupled to each datareceiver to provide trip point adjustment information to the trip pointadjustor of each data receiver, the data corrector including: a firstancillary data receiver having a first trip point adjustor; a secondancillary data receiver having a second trip point adjustor; acontroller coupled to the first trip point adjustor of the firstancillary data receiver and coupled to the second trip point adjustor ofthe second ancillary data receiver to provide trip point adjustmentvectors.
 18. The electronic apparatus of claim 17, including a latchcoupled between the data corrector and each data receiver of theplurality of data receivers to conditionally provide the trip pointadjustment information from the data corrector to the trip pointadjustor of each data receiver.
 19. The electronic apparatus of claim18, wherein data corrector is structured to provide the trip pointadjustment information conditioned on the trip point adjustment vectorsprovided to the first and second ancillary data receivers without changefor a number of adjustment cycles.
 20. The electronic apparatus of claim17, wherein the electronic apparatus includes a processor.
 21. A memorycomprising: a data receiver, the data receiver having a receiver with atrip point and having a trip point adjustor; and a data correctorcoupled to the data receiver to provide trip point adjustmentinformation to the trip point adjustor of the data receiver, the datacorrector including: a first ancillary data receiver having a first trippoint adjustor; a second ancillary data receiver having a second trippoint adjustor; a phase detector coupled to an output of the firstancillary data receiver and coupled to an output of the second ancillarydata receiver, wherein the phase detector is arranged to compare anoutput signal of the first ancillary data receiver with an output signalfrom the second ancillary data receiver; and a controller coupled to thephase detector, coupled to the first trip point adjustor of the firstancillary data receiver, and coupled to the second trip point adjustorof the second ancillary data receiver.
 22. The memory of claim 21,wherein the memory includes a filter, the filter coupled to and betweenthe phase detector and the controller.
 23. The memory of claim 22,wherein the filter is coupled to the first ancillary data receiver andto the second ancillary data receiver.
 24. The memory of claim 21,wherein the memory includes a latch, the latch coupled to and betweenthe data receiver and the data corrector.
 25. The memory of claim 24,wherein the latch is coupled to the controller.
 26. An electronicapparatus comprising: a plurality of series configured n-type MOStransistor pairs coupled between a node and ground; and a plurality ofseries configured p-type MOS transistor pairs coupled between a firstvoltage and the node, wherein the plurality of series configured n-typeMOS transistor pairs and the plurality of series configured p-type MOStransistor pairs are configured to adjust a voltage at the node.
 27. Theelectronic apparatus of claim 26, wherein the plurality of seriesconfigured n-type MOS transistor pairs is four, and the plurality ofseries configured p-type MOS transistor pairs is four.
 28. Theelectronic apparatus of claim 26, wherein the plurality of seriesconfigured n-type MOS transistor pairs include a weighted set of seriesconfigured n-type MOS transistor pairs, and the plurality of seriesconfigured p-type MOS transistor pairs include a weighted set of seriesconfigured p-type MOS transistor pairs.
 29. The electronic apparatus ofclaim 28, wherein the weighted set of series configured n-type MOStransistor pairs and the weighted set of series configured p-type MOStransistor pairs are weighted based on a width to a length ratio foreach n-type MOS transistor acting as a load transistor in the seriesconfigured n-type MOS transistor pairs and for each p-type MOStransistor acting as a load transistor in the series configured p-typeMOS transistor pairs.
 30. An electronic apparatus comprising: a firstancillary data receiver; a second ancillary data receiver; and acontroller coupled to the first ancillary data receiver and coupled tothe second ancillary data receiver to provide adjustment vectors to thefirst ancillary data receiver and to the second ancillary data receiver.31. The electronic apparatus of claim 30, wherein the first ancillarydata receiver has a first structure, the second ancillary data receiverhas a second structure, the first structure correlated to the secondstructure.
 32. The electronic apparatus of claim 30, wherein thecontroller includes control logic to send the adjustment vectors to datareceivers external to the to the first and second ancillary datareceivers after determining that the adjustment vectors have beenprovided to the first and second ancillary data receivers without changefor a number of adjustment cycles.
 33. The electronic apparatus of claim30, wherein the adjustment vectors to the first ancillary data receiverand to the second ancillary data receiver provide signals to adjust trippoints of the first ancillary data receiver and the second ancillarydata receiver.
 34. The electronic apparatus of claim 30, wherein thefirst ancillary data receiver includes a data port configured forreceiving a first clock signal, the second ancillary data receiverincludes a data port configured for receiving a second clock signal, thefirst ancillary data receiver coupled to the second ancillary datareceiver at a voltage reference port capable of receiving a referencevoltage.
 35. The electronic apparatus of claim 30, wherein theelectronic apparatus includes a phase detector coupled to an output ofthe first ancillary data receiver and coupled to an output of the secondancillary data receiver, wherein the phase detector is configured tocompare an output signal of the first ancillary data receiver with anoutput signal from the second ancillary data receiver.
 36. Theelectronic apparatus of claim 35, wherein the electronic apparatusincludes a filter coupled between the phase detector and the controller,the filter to control an output signal from the phase detector to thecontroller based on a predetermined setting.
 37. The electronicapparatus of claim 36, wherein the filter includes a counter todetermine whether the output of the phase detector has maintained aconstant level for a plurality of clock pulses.
 38. The electronicapparatus of claim 36, wherein the plurality of clock pulses is four.39. An electronic apparatus comprising: a first ancillary data receiverhaving a first trip point adjustor; a second ancillary data receiverhaving a second trip point adjustor; a phase detector coupled to anoutput of the first ancillary data receiver and coupled to an output ofthe second ancillary data receiver; and a controller coupled to thephase detector, the controller coupled to the first and second trippoint adjustors to provide trip point adjustment vectors to the firsttrip point adjustor and to the second trip point adjustor.
 40. Theelectronic apparatus of claim 39, wherein the first ancillary datareceiver includes a data port configured for receiving a first clocksignal, the second ancillary data receiver includes a data portconfigured for receiving a second clock signal, the first ancillary datareceiver coupled to the first ancillary data receiver at a voltagereference port capable of receiving a reference voltage.
 41. Theelectronic apparatus of claim 39, wherein the electronic apparatusfurther includes a filter coupled between the phase detector and thecontroller, coupled to the first ancillary data receiver and coupled tothe first ancillary data receiver.
 42. The electronic apparatus of claim39, wherein the controller includes control logic to send the adjustmentvectors to data receivers external to the data corrector after adetermination that the adjustment vectors have been provided to thefirst and second trip point adjustors without change for a number ofadjustment cycles.
 43. A phase detector comprising: a means forbalancing two signals; and a means for comparing a zero crossing of thetwo signals, the means for balancing two signals coupled to the meansfor comparing a zero crossing of the two signals.
 44. The phase detectorof claim 43, wherein a means for comparing a zero crossing of the twosignals includes circuitry to determine when a transition of a risingedge on one signal is concurrent with a transition of a falling edge ofthe other signal.
 45. The phase detector of claim 43, wherein the meansfor balancing two signals includes: a first NAND gate having an output;a second NAND gate having an output; a first n-type capacitor coupledbetween ground and the output of the first NAND gate; a second n-typecapacitor coupled between ground and the output of the second NAND gate;a first inverter coupled to the output of the first NAND gate; a secondinverter coupled to the output of the second NAND gate; a third n-typecapacitor coupled between ground and an output of the first inverter; afourth n-type capacitor coupled between ground and an output of thesecond inverter; and a p-type capacitor coupled between a voltage andthe output of the first inverter, wherein the n-type and p-typecapacitors have capacitances set such that, for a first clock signal atan input to the first NAND gate and a second clock signal at an input tothe second NAND gate, a rise time and a fall time for the first clock atan output of the first inverter is approximately equal to a rise timeand a fall time for the second clock at an output of the secondinverter.
 46. The phase detector of claim 43, wherein the means forcomparing a zero crossing of the two signals includes: a NAND gatehaving an output coupled to a first inverter; and a NOR gate having anoutput coupled to a second inverter, the second inverter having anoutput coupled to an input of the NAND gate, an input of the NOR gatecoupled to an output of the first inverter.
 47. The phase detector ofclaim 46, wherein the means for comparing a zero crossing of the twosignals includes: a third inverter coupled to the output of the NANDgate; a fourth inverter coupled in series to the output of the thirdinverter; a fifth inverter coupled to the output of the NOR gate; afirst p-type MOS transistor coupled in series with the output of thefourth inverter; a first n-type MOS transistor coupled between the firstp-type MOS transistor and a node, a gate of the first p-type MOStransistor coupled to a gate of the first n-type MOS transistor, thegate of the first p-type MOS transistor coupled to an output of thefifth inverter; a second p-type MOS transistor coupled in series withthe output of the fifth inverter; and a second n-type MOS transistorcoupled between the second p-type MOS transistor and the node, a gate ofthe second p-type MOS transistor coupled to a gate of the second n-typeMOS transistor, the gate of the second p-type MOS transistor coupled toan output of the fourth inverter.
 48. A balancing circuit comprising: afirst NAND gate having an output; a second NAND gate having an output; afirst n-type capacitor coupled between ground and the output of thefirst NAND gate; a second n-type capacitor coupled between ground andthe output of the second NAND gate; a first inverter coupled to theoutput of the first NAND gate; a second inverter coupled to the outputof the second NAND gate; a third n-type capacitor coupled between groundand an output of the first inverter; a fourth n-type capacitor coupledbetween ground and an output of the second inverter; and a p-typecapacitor coupled between a voltage and the output of the firstinverter, wherein the n-type and p-type capacitors have capacitances setsuch that, for a first clock signal at an input to the first NAND gateand a second clock signal at an input to the second NAND gate, a risetime and a fall time for the first clock at an output of the firstinverter is approximately equal to a rise time and a fall time for thesecond clock at an output of the second inverter.
 49. A phase detectioncircuit comprising: a NAND gate having an output coupled to a firstinverter; and a NOR gate having an output coupled to a second inverter,the second inverter having an output coupled to an input of the NANDgate, an input of the NOR gate coupled to an output of the firstinverter.